1. Field of the Invention
This invention pertains in general to a non-volatile memory device and, more particularly, to a sensing circuit of a non-volatile memory device.
2. Description of the Related Art
Sensing circuits, or sense amplifiers, are commonly used in non-volatile memory devices to ascertain the binary states of the devices. For example, U.S. Pat. No. 5,386,158 ("the '158 patent") discloses a sensing circuit for a floating-gate memory device.
FIG. 1 shows a portion of the circuitry illustrated in FIG. 2a of the '158 patent. Referring to FIG. 1, the '158 patent discloses a sensing circuit 10 comprised of primarily MOS transistors. Sensing circuit 10 is coupled to a memory array 12 that includes a plurality of non-volatile memory cells 12a, 12b . . . 12n, only one of which (12a) is shown. Memory array 12 is connected to a sensing line 80 through a multiplexer 16. Sensing line 80 connects to the gate of an n-type transistor 36. The source of transistor 36 is connected to a ground potential and the drain is connected to the source of an n-type transistor 34. The terms "source" and "drain," as well known in the art, can be used interchangeably. The drain and gate of transistor 34 are connected together and also to the drain of a p-type transistor 32. The gate of transistor 32 is connected to a reference potential V.sub.REF, and the source is connected to a voltage potential V.sub.c. Transistors 32, 34, and 36 operate as a voltage amplifier.
The gate and drain of transistor 34 are also connected to the gate of an n-type transistor 44. The drain of transistor 44 is connected to the drain and the gate of a p-type transistor 40 and also the gate of a p-type transistor 42. The source of transistor 40 and the source of transistor 42 are connected to voltage potential V.sub.c. Transistors 40, 44, and 42 operate as a current mirror. The drain of transistor 42 is connected to the input of an inverter 28 and the drain of an n-type transistor 48. The source of transistor 48 is connected to a ground potential and the gate is connected to a reference voltage V.sub.SENREF. Inverter 28 provides an output S.sub.OUT.
Sensing line 80 is additionally connected to the drain and the gate of an n-type transistor 46. The drain and the gate of transistor 46 are also connected to the source of transistor 44. The source of transistor 46 is connected to a ground potential.
As described by the '158 patent, transistors 34 and 44 will be on regardless of the conductive state of the memory cell being sensed, for example, memory cell 12a. When memory cell 12a is in a conductive state, transistor 34 generates a first voltage to maintain the voltage at sensing line 80. Current then flows from transistor 40, through transistor 44, to sensing line 80 to maintain the conductive state of memory cell 12a. When memory cell 12a is in a non-conductive state, there is no current flow in sensing line 80 initially. Because transistor 44 is on, the voltage on sensing line 80 will subsequently be charged up. When the voltage on sensing line 80 increases, the voltage at the gate of transistor 34 drops, generating a second voltage. Transistor 40 continues to supply current to sensing line 80 through transistor 44 until sensing line 80 reaches a saturation level, at which point transistor 46, also known as a "leaker," conducts excess current to ground to prevent the voltage on sensing line 80 from cutting off transistor 44.
The sensing operation is conducted through transistors 40, 42, 48 and inverter 28. Depending upon the net current flow into or out from the input of inverter 28, S.sub.OUT will either be high or low. Because the current flow through transistor 42 mirrors the current flow through transistor 40, the current flow to the input of inverter 28 also mirrors the current flow through transistor 40. The '158 patent additionally describes how reference voltage V.sub.SENREF is generated from which the net current flow into inverter 28 is determined. The '158 patent is hereby incorporated by reference.
When sensing circuit 10 is first enabled, transistors 40 and 42 are operating in the cut-off region. If V.sub.SENREF is provided to transistor 48, which turns transistor 48 on, while transistors 40 and 42 are off, output signal S.sub.OUT will be pulled to zero, creating a transition output noise. Damping noise may also be created during the same period between transistors 40 and 42 as transistor 42 generates a current that "mirrors" the charging current through transistor 40. In addition, because only one current path, namely the one through transistors 40 and 44, is provided to sensing line 80, insufficient charging current is provided to bring sensing circuit 10 from the cut-off region into its linear operating region within a short enough period of time to avoid transition noises or to allow sensing circuit 10 to provide high sensing speed.